Practical Low Power Digital VLSI Design emphasizes the optimization and trade-off techniques that involve power dissipation, in the hope that the readers are better prepared the next time they are presented with a low power design problem. The book highlights the basic principles, methodologies and techniques that are common to most CMOS digital designs. The advantages and disadvantages of a particular low power technique are discussed. Besides the classical area-performance trade-off, the impact to design cycle time, complexity, risk, testability and reusability are discussed. The wide impacts to all aspects of design are what make low power problems challenging and interesting. Heavy emphasis is given to top-down structured design style, with occasional coverage in the semicustom design methodology. The examples and design techniques cited have been known to be applied to production scale designs or laboratory settings. The goal of Practical Low Power Digital VLSI Design is to permit the readers to practice the low power techniques using current generation design style and process technology. Practical Low Power Digital VLSI Design considers a wide range of design abstraction levels spanning circuit, logic, architecture and system. Substantial basic knowledge is provided for qualitative and quantitative analysis at the different design abstraction levels. Low power techniques are presented at the circuit, logic, architecture and system levels. Special techniques that are specific to some key areas of digital chip design are discussed as well as some of the low power techniques that are just appearing on the horizon. Practical Low Power Digital VLSI Design will be of benefit to VLSI design engineers and students who have a fundamental knowledge of CMOS digital design.
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With increasing demand of System on Chip, the number of transistors also getting increased in VLSI chip, which causes high power dissipation. Now a days the demand of portable devices like smart phones, PDAs, tablet PC also increasing, therefore low power designing has become a key parameter. More power dissipation also causes heating up the device which reduces the performance, reliability and durability. Hence the need of the low power VLSI circuit arises, so leakage power needs to be reduced.
This technique compromise between the high performance and low leakage power. Transistors those are located on critical paths are assigned as low threshold voltage and the transistors that are not critical to timing can tolerate high threshold voltages and slow switching speeds. The selection of the control voltages are conducted at design times, no additional circuits are required. The below table shows the leakage current for high and low threshold voltage transistors in a 70nm process technology. We observe that leakage energy of transistors of low threshold voltage is larger than a factor of 75 than the high threshold voltage transistors. Hence if we replace the low Vt transistor with a high Vt transistor it will reduce the energy or power.
We reviewed various sources of leakage current in CMOS circuit and described a number of reduction techniques for controlloing the leakage current. In a way of enumarating some of the design and conclusion that lie ahead,necessity of robust subthreshold leakage control techniques that do not affect circuit performance and devlopment of physical design tools that support multiple voltages on the chip. There is a need of more advanced technique to reduce the power consumption while maintaining the chip perforamance.
Prefacetion problem in all application areas. It is also my observation that power efficiencycannot be achieved without affecting the other figures of merits of the design. Thisbook emphasizes the optimization and trade-off techniques that involve power dissi-pation, in the hope that the readers are better prepared the next time they are presentedwith a low power design problem. It does not document particular results collectedfrom some low power design projects. Rather, it highlights the basic principles, meth-odologies and techniques that are common to most CMOS digital designs. The advan-tages and disadvantages of a particular low power technique will be discussed.Besides the classical area-performance trade-off, the impact to design cycle time,complexity, risk, testability, reusability will be discussed. The wide impacts to allaspects of design are what make the low power problems challenging and interesting.Heavy emphasis will be given to top-down structured design style with occasion cov-erage in the semicustom design methodology. The examples and design techniquescited have been known to be applied to production scale designs or laboratory set-tings. The goal is to permit the readers to practice the low power techniques usingcurrent generation design style and process technology.Today, the VLSI design task is so huge that specialization is a must. As a result, mostdesigners are experienced in their corresponding focused areas. However, the lowpower problem is one that calls for total solution at all levels of design abstraction toachieve the highest impact. A design decision made at one level of abstraction canhamper or aid the low power goal in the downstream design process. A breadth ofknowledge from all aspects of the design from specification to mass production isrequired. Hopefully, this book can provide a comprehensive coverage in all areas ofthe digital design domain. Some analysis techniques have been so mature that com-mercial Computer-Aided Design software packages have routinely been used in thedesign process. This book will illuminate the application and the potential role of thesoftware in solving low power problems.The book is intended to cover wide ranges of design abstraction levels spanning cir-cuit, logic, architecture and system. The art of chip design demands solid intuition,skill and experience. If the craftsmanship of chip design can be acquired through hardwork, I believe the basic drill is in the qualitative and quantitative analysis at the vari-ous levels of design abstraction. The first three chapters provide enough basic knowl-edge to cover the qualitative and quantitative analysis at the different designabstraction levels. It is recommended that Chapter 1 thorough 3 be read, in succes-sion, before the later chapters. Subsequent chapters present the low power techniquesat the circuit, logic, architecture and system levels. Chapter 6 includes special tech-niques that are specific to some key areas of digital chip design. The last chapter pro-vides a glimpse of the low power techniques appearing on the horizon.vi
1 Introductionrate analysis results are expected and tolerated. As the design proceeds to reveal morelower-level details, a more accurate analysis can be performed. Here, better accuracyis demanded and longer analysis time is allowed.Analysis techniques also serve as the foundation for design optimization. Optimiza-tion is the process of generating the best design, given an optimization goal, withoutviolating design specifications. An automatic design optimization algorithm requiresa fast analysis engine to evaluate the merits of the design choices. Manual optimiza-tion also demands a reliable analysis tool to provide accurate estimation of power dis-sipation. A decision to apply a particular low power technique often involves trade-offs from different sources pulling in various directions. Major criteria to be consid-ered are the impact to the circuit delay, which affects the performance and throughputof the chip, and the chip area, which directly translates to manufacturing costs. Otherfactors of chip design such as design cycle time, testability, quality, reliability, reus-ability, risk, etc., may all be affected by a particular design decision to achieve the lowpower requirement. Power efficiency cannot be achieved without yielding to one ormore of these factors. The task of a design engineer is to carefully weigh each designchoice within the specification constraints and select the best implementation.This chapter starts with a brief introduction to the driving forces behind the lowpower needs. Before we set out to analyze or optimize the power dissipation of aVLSI chip, the basic understanding of the fundamental circuit theory of power dissi-pation is imminent. Section 1 to 1 is a summary of the basic power dissipationmodes of a digital chip. We will emphasize the qualitative effects of the power dissi-pation common to all digital circuits. We shall assume that the readers are familiarwith the basic steps of CMOS digital VLSI design, in particular, circuit and logicdesign, cell library, logic synthesis and commonly used subsystems such as RAMs,adders, multipliers, etc. A good introduction to CMOS VLSI design is given by Westeand Eshraghian [1].1 Needs/or Low Power VLS1 ChipsPower dissipation of VLSI chips is traditionally a neglected subject. In the past, thedevice density and operating frequency were low enough that it was not a constrain-ing factor in the chips. As the scale of integration improves, more transistors, fasterand smaller than their predecessors, are being packed into a chip. This leads to thesteady growth of the operating frequency and processing capacity per chip, resultingin increased power dissipation.2
There are various interpretations of the Moore s Law that predicts the growth rate of integrated circuits. One estimate places the rate at 2X for every eighteen months. Oth- ers claim that the device density increases ten-fold every seven years. Regardless of the exact numbers, everyone agrees that the growth rate is rapid with no signs of slowing down. New generations of processing technology are being developed while present generation devices are at a very safe distance from the fundamental physical limits. A need for low power VLSI chips arises from such evolution forces of integra- tion circuits. Another factor that fuels the needs for low power chips is the increased market demand for portable consumer electronics powered by batteries. The craving for smaller, lighter and more durable electronic products indirectly translates to low power requirements. Battery life is becoming a product differentiator in many porta- ble electronic markets. Being the heaviest and biggest component in many portable systems, batteries have not experienced the similar rapid density growth compared to electronic circuits. The specific weight (stored energy per unit weight) of batteries barely doubles in several years. Besides technological issues, further increase in bat- tery specific weight will soon draw safety concerns because the energy density is approaching that of explosive chemicals. It has been generally concluded that the bat- tery technology alone will not solve the low power problem in the near future. Ironically, high performance computing system characterized by large power dissipa- tion also drives the low power needs. The power dissipation of high performance microprocessors is now approaching several dozen Watts [1], comparable to that of a hand-held soldering iron. Power dissipation has a direct impact on the packaging cost of the chip and the cooling cost of the system. Some personal computer's CPUs require cooling fans directly mounted on the chip carriers due to the high power dissi- pation. A chip that operates at 3 consuming lOW means that the average current is 3A. The transient current could be several times larger than the average current. This creates problems in the design of power supply rails and poses big challenges in the analysis of digital noise immunity. Another major demand for low power chips and systems comes from environmental concerns. Modem offices are now furnished with office automation equipment that consume large amount of power. A study by American Council for an Energy-Effi- cient Economy estimated that office equipment account for 5% of total US commer- cial energy usage in 1993 and could rise to 10% by the year 2000 if no actions are taken to prevent the trend [1]. Computers are the fastest-growing electricity loads in the commercial sector. Since electricity generation is a major source of air pollution, inefficient energy usage in computing equipment indirectly contributes to environ- mental pollution. The problem has prompted The US Environmental Protection Agency and The US Department of Energy to promote the Energy Star program [1] 3 2ff7e9595c
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